• Top
  • Documentation
  • Books
  • Boolean-reasoning
  • Projects
  • Debugging
  • Std
  • Proof-automation
  • Macro-libraries
  • ACL2
  • Interfacing-tools
  • Hardware-verification
    • Gl
    • Esim
    • Vl2014
    • Sv
      • Svex-stvs
        • Svtv-data
          • Defsvtv$
          • Defcycle
          • Def-pipeline-thm
          • Def-svtv-data-export
          • Def-svtv-data-import
          • Svtv-name-lhs-map
            • Svtv-name-lhs-map-fix
            • Svtv-name-lhs-map-p
            • Svtv-namemap->lhsmap
            • Svtv-name-lhs-map-equiv
            • Svtv-namemap
          • Def-cycle-thm
          • Def-svtv-data-export/import
          • Defsvtv$-phasewise
        • Defsvtv$
        • Svtv-run
        • Defsvtv-phasewise
        • Svtv
        • Svtv-spec
        • Defsvtv
        • Process.lisp
        • Svtv-doc
        • Svtv-chase$
        • Svtv-versus-stv
        • Svtv-debug-fsm
        • Structure.lisp
        • Svtv-debug
        • Def-pipeline-thm
        • Expand.lisp
        • Def-cycle-thm
        • Svtv-utilities
        • Svtv-debug$
        • Defsvtv$-phasewise
      • Svex-decomposition-methodology
      • Sv-versus-esim
      • Svex-decomp
      • Svex-compose-dfs
      • Svex-compilation
      • Moddb
      • Svmods
      • Svstmt
      • Sv-tutorial
      • Expressions
      • Symbolic-test-vector
      • Vl-to-svex
    • Vwsim
    • Fgl
    • Vl
    • X86isa
    • Svl
    • Rtl
  • Software-verification
  • Math
  • Testing-utilities

• Svtv-data

Svtv-name-lhs-map

Mapping from user-provided names (generally symbols) to normalized internal names.

See svtv-namemap->lhsmap.

Subtopics

Svtv-name-lhs-map-fix

(svtv-name-lhs-map-fix x) is an fty alist fixing function that follows the drop-keys strategy.

Svtv-name-lhs-map-p

Recognizer for svtv-name-lhs-map.

Svtv-namemap->lhsmap

Processes a list of nicknames for SystemVerilog-syntax signals into an internal form.

Svtv-name-lhs-map-equiv

Basic equivalence relation for svtv-name-lhs-map structures.

Svtv-namemap

A mapping from user-provided names (generally symbols) to signal names in SystemVerilog hierarchical syntax (strings).