• Top
    • Documentation
    • Books
    • Boolean-reasoning
    • Projects
    • Debugging
    • Std
    • Community
    • Proof-automation
    • ACL2
    • Macro-libraries
    • Interfacing-tools
    • Hardware-verification
      • Gl
      • Esim
      • Vl2014
        • Warnings
        • Primitives
        • Use-set
        • Syntax
        • Getting-started
        • Utilities
        • Loader
        • Transforms
          • Expression-sizing
          • Occform
            • Vl-mux-occform
            • Vl-basic-binary-op-occform
            • Vl-occform-mkports
            • Vl-unary-reduction-op-occform
            • Vl-make-n-bit-mux
            • Vl-bitselect-occform
            • Vl-assign-occform
            • Vl-plusminus-occform
            • Vl-shift-occform
            • Vl-gte-occform
            • Vl-plain-occform
            • Vl-unary-not-occform
            • Vl-rem-occform
            • Vl-div-occform
            • Vl-ceq-occform
            • Vl-mult-occform
            • Vl-make-n-bit-dynamic-bitselect-m
            • Vl-simple-instantiate
            • Vl-occform-mkwires
            • Vl-assignlist-occform
            • Vl-occform-argfix
            • Vl-make-n-bit-unsigned-gte
            • Vl-make-2^n-bit-dynamic-bitselect
            • Vl-make-n-bit-div-rem
            • Vl-make-n-bit-plusminus
            • Vl-make-n-bit-signed-gte
            • Vl-make-n-bit-shr-by-m-bits
            • Vl-make-n-bit-shl-by-m-bits
            • Vl-occform-mkport
            • Vl-make-n-bit-dynamic-bitselect
            • Vl-make-n-bit-reduction-op
            • Vl-make-n-bit-adder-core
            • Vl-make-n-bit-xdetect
            • Vl-make-n-bit-x-propagator
            • Vl-make-n-bit-shl-place-p
            • Vl-make-n-bit-shr-place-p
            • Vl-make-n-bit-mult
            • Vl-occform-mkwire
            • Vl-make-nedgeflop-vec
            • Vl-make-n-bit-binary-op
            • Vl-make-list-of-netdecls
            • Vl-make-n-bit-delay-1
            • Vl-make-n-bit-zmux
            • *vl-2-bit-dynamic-bitselect*
            • Vl-make-n-bit-unsigned-rem
            • Vl-make-n-bit-unsigned-div
            • Vl-make-n-bit-shr-place-ps
            • Vl-make-n-bit-shl-place-ps
            • Vl-make-n-bit-assign
            • Vl-make-n-bit-x
            • Vl-make-n-bit-ceq
              • Vl-make-n-bit-xor-each
              • Vl-make-n-bit-not
              • Vl-make-1-bit-delay-m
              • Vl-make-n-bit-delay-m
              • *vl-1-bit-signed-gte*
              • *vl-1-bit-div-rem*
              • *vl-1-bit-adder-core*
              • Vl-make-nedgeflop
              • *vl-1-bit-mult*
              • *vl-1-bit-dynamic-bitselect*
            • Oprewrite
            • Expand-functions
            • Delayredux
            • Unparameterization
            • Caseelim
            • Split
            • Selresolve
            • Weirdint-elim
            • Vl-delta
            • Replicate-insts
            • Rangeresolve
            • Propagate
            • Clean-selects
            • Clean-params
            • Blankargs
            • Inline-mods
            • Expr-simp
            • Trunc
            • Always-top
            • Gatesplit
            • Gate-elim
            • Expression-optimization
            • Elim-supplies
            • Wildelim
            • Drop-blankports
            • Clean-warnings
            • Addinstnames
            • Custom-transform-hooks
            • Annotate
            • Latchcode
            • Elim-unused-vars
            • Problem-modules
          • Lint
          • Mlib
          • Server
          • Kit
          • Printer
          • Esim-vl
          • Well-formedness
        • Sv
        • Fgl
        • Vwsim
        • Vl
        • X86isa
        • Svl
        • Rtl
      • Software-verification
      • Math
      • Testing-utilities
    • Occform

    Vl-make-n-bit-ceq

    Generate a wide case-equality module.

    Signature
    (vl-make-n-bit-ceq n) → mods
    Arguments
    n — Guard (posp n).
    Returns
    mods — A non-empty module list. The first module in the list is the desired module; the other modules are any necessary supporting modules.
        Type (vl-modulelist-p mods).

    We generate a module that is written using gates and which is semantically equivalent to:

    module VL_N_BIT_CEQ (out, a, b) ;
      output out;
      input [N-1:0] a;
      input [N-1:0] b;
      assign out = (a === b);
    endmodule

    We basically just instantiate *vl-1-bit-ceq* N times and then reduction-and the results.

    Definitions and Theorems

    Function: vl-make-n-bit-ceq

    (defun vl-make-n-bit-ceq (n)
     (declare (xargs :guard (posp n)))
     (declare (xargs :guard t))
     (let ((__function__ 'vl-make-n-bit-ceq))
       (declare (ignorable __function__))
       (b*
        ((n (lposfix n))
         ((when (eql n 1)) (list *vl-1-bit-ceq*))
         (name (hons-copy (cat "VL_" (natstr n) "_BIT_CEQ")))
         ((mv out-expr
              out-port out-portdecl out-vardecl)
          (vl-occform-mkport "out" :vl-output 1))
         ((mv a-expr a-port a-portdecl a-vardecl)
          (vl-occform-mkport "a" :vl-input n))
         ((mv b-expr b-port b-portdecl b-vardecl)
          (vl-occform-mkport "b" :vl-input n))
         ((mv tmp-expr tmp-vardecl)
          (vl-occform-mkwire "tmp" n))
         (tmp-wires (vl-make-list-of-bitselects tmp-expr 0 (- n 1)))
         (a-wires (vl-make-list-of-bitselects a-expr 0 (- n 1)))
         (b-wires (vl-make-list-of-bitselects b-expr 0 (- n 1)))
         (insts (vl-simple-inst-list *vl-1-bit-ceq*
                                     "bit" tmp-wires a-wires b-wires))
         (and-mods (vl-make-n-bit-reduction-op :vl-unary-bitand n))
         (and-mod (car and-mods))
         (and-inst (vl-simple-inst and-mod "mk_out" out-expr tmp-expr)))
        (list* (make-vl-module
                    :name name
                    :origname name
                    :ports (list out-port a-port b-port)
                    :portdecls (list out-portdecl a-portdecl b-portdecl)
                    :vardecls (list out-vardecl
                                    a-vardecl b-vardecl tmp-vardecl)
                    :modinsts (append insts (list and-inst))
                    :minloc *vl-fakeloc*
                    :maxloc *vl-fakeloc*)
               *vl-1-bit-ceq* and-mods))))

    Theorem: vl-modulelist-p-of-vl-make-n-bit-ceq

    (defthm vl-modulelist-p-of-vl-make-n-bit-ceq
      (b* ((mods (vl-make-n-bit-ceq n)))
        (vl-modulelist-p mods))
      :rule-classes :rewrite)

    Theorem: type-of-vl-make-n-bit-ceq

    (defthm type-of-vl-make-n-bit-ceq
      (and (true-listp (vl-make-n-bit-ceq n))
           (consp (vl-make-n-bit-ceq n)))
      :rule-classes :type-prescription)

    Theorem: vl-make-n-bit-ceq-of-pos-fix-n

    (defthm vl-make-n-bit-ceq-of-pos-fix-n
      (equal (vl-make-n-bit-ceq (pos-fix n))
             (vl-make-n-bit-ceq n)))

    Theorem: vl-make-n-bit-ceq-pos-equiv-congruence-on-n

    (defthm vl-make-n-bit-ceq-pos-equiv-congruence-on-n
      (implies (acl2::pos-equiv n n-equiv)
               (equal (vl-make-n-bit-ceq n)
                      (vl-make-n-bit-ceq n-equiv)))
      :rule-classes :congruence)