Vl-regularport
Representation of a single non-interface port.
This is a product type introduced by defprod.
Fields
- name — maybe-string
- The "externally visible" name of this port, for use in named module
instances. Usually it is best to avoid this; see below.
- expr — vl-maybe-expr
- How the port is wired internally within the module. Most of the time,
this is a simple identifier expression that is just name. But
it can also be more complex; see below. The expression should be
nil for interface ports.
- loc — vl-location
- Where this port came from in the Verilog source code.
In Verilog-2005, ports are described in Section 12.3 of the
standard.
It is important to understand the difference between ports and port
declarations. We represent ports as vl-port structures, whereas port
declarations re represented as vl-portdecl structures. It is easy to
see the difference between ports and port declarations when modules are
declared using the "non-ANSI" syntax.
module mod(a,b,c) ; <-- ports
input [3:0] a; <-- port declarations (not ports)
input b;
output c;
endmodule
It is less easy to see this difference when the more concise "ANSI" syntax
is used:
module mod(
input [3:0] a; <-- ports and port declarations, mixed together
input b;
output c;
) ;
...
endmodule
Regardless of which syntax is used, VL internally creates both ports and
portdecls as separate structures.
In most designs, there is a single port corresponding to each port
declaration. However, in general Verilog permits more complex ports. Here is
an example of a module where the ports have external names that are distinct
from their internal wiring.
module mod (a, .b(w), c[3:0], .d(c[7:4])) ;
input a;
input w;
input [7:0] c;
...
endmodule
In this example, the names of these ports would be, respectively:
"a", "b", nil (because the third port has no externally
visible name), and "d". Meanwhile, the first two ports are internally
wired to a and w, respectively, while the third and fourth ports
collectively specify the bits of c.
SystemVerilog-2012 extends ports in several ways, but most of these
extensions (e.g., support for fancy data types) are related to the port
declarations rather than the ports. One place where the ports themselves
are extended is for interface ports. See vl-port.
Subtopics
- Vl-regularport-fix
- Fixing function for vl-regularport structures.
- Vl-regularport-equiv
- Basic equivalence relation for vl-regularport structures.
- Vl-regularport-p
- Recognizer for vl-regularport structures.
- Make-vl-regularport
- Basic constructor macro for vl-regularport structures.
- Vl-regularport->name
- Get the name field from a vl-regularport.
- Vl-regularport->loc
- Get the loc field from a vl-regularport.
- Vl-regularport->expr
- Get the expr field from a vl-regularport.
- Change-vl-regularport
- Modifying constructor for vl-regularport structures.
