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Substitution into Verilog constructs
We implement routines to substitute values for identifiers throughout Verilog constructs such as expressions, assignments, and modules.
Our original use of substitution was in unparameterization, where we used substitution to replace parameters with their values throughout a module. Because of this, and since there are usually only a couple of parameters per module, we historically created ordinary alists and look up with hons-assoc-equal rather than hons-get. Since then we have found substitution to be more generally useful, and prefer to use fast alists.