A New Formulation of Neural Data
Prefetching
with Q. Duong and A. Jain.
International Symposium on Computer Architecture (ISCA),
2024
Tail Victims in Termination Timing
Channel Protections beyond Cryptographic Kernels
with S. Wei, A. Harris, Y. Zhu, P. Ramrakhyani, and M. Tiwari,
International Symposium on Secure and Private Execution Environment Design (SEED),
2024
Leveraging Domain Information for the
Efficient, Automated Design of Deep Learning Accelerators,
with C. Sakhuja and Z. Shi,
International Symposium on High-Performance Computer Architectural (HPCA),
2023
Effective Mimicry of Belady's MIN Policy
with I. Shah and A. Jain,
International Symposium on High-Performance Computer Architectural (HPCA),
2022
(Micro Top Picks 2023)
(Finalist, Best Paper Award)
A Hierarchical Neural Model of Data
Prefetching
with Z. Shi, A. Jain, K. Swersky, M. Hashemi, and P. Raganathan,
International Conference on Architectural Support for Programming Languages
and Operating Systems (ASPLOS),
2021
(Micro Top Picks Honorable Mention)
A Fast Work-Efficient SSSP Algorithm
for GPUs
with K. Wang and D. Fussell,
26th Annual Symposium on Principles and Practice of Parallel Programming
(PPoPP),
2021
Combining Branch History and Value History
For Improved Value Prediction,
with C. Sakhuja, A. Subramanian, P. Joshi, and A. Jain,
2nd Championship Value Prediction (Top Place Unlimited Category),
2019
Temporal Prefetching without the Off-Chip Metadata
with H. Wu, K. Nathella, J. Pusdesris, D. Sunwoo, and A. Jain,
52nd International Symposium on Microrchitecture (MICRO),
2019, pp. 996-1008.
Applying Deep Learning to the Cache Replacement Problem
with Z. Shi, X. Huang, and A. Jain,
52nd International Symposium on Microrchitecture (MICRO),
2019, pp. 413-425.
Efficient Metadata Management for Irregular Data Prefetching
with H. Wu, K. Nathella, D. Sunwoo, and A. Jain
46th International Symposium on Computer Architecture (ISCA),
2019, pp. 449-461.
Fast Fine-Grained Global
Synchronization on GPUs
with K. Wang and D. Fussell
24th International Conference on Architectural Support for Programming
Languages and Operating Systems (ASPLOS)
2019, pp. 793-806.
Rethinking Belady's
Algorithm to Accommodate Prefetching
with A. Jain
45th International Symposium on Computer Architecture (ISCA),
2018, pp. 110-123.
Hawkeye: Leveraging Belady's Algorithm
for Improved Cache Replacement
with A. Jain
2nd Cache Replacement Competition,
2017.
(First Place Finisher)
Decoupled Affine Computation for SIMT GPUs
with K. Wang
44th International Symposium on Computer Architecture (ISCA),
2017, pp. 295--306.
Secure, Precise, and Fast Floating-Point
Operations on x86 Processors
with A. Rane and M. Tiwari
25th USENIX Security Symposium (USENIX Security)
2016, pp. 71-86.
Back to the Future: Leveraging Belady's
Algorithm for Improved Cache Replacement
with A. Jain
43th International Symposium on Computer Architecture (ISCA),
2016, pp. 78-89.
(Micro Top Picks Honorable Mention)
Raccoon: Closing Digital Side-Channels
through Obfuscated Execution
with A. Rane and M. Tiwari
USENIX Security Symposium,
2015, pp. 431-446.
Linearizing Irregular Memory Accesses
for Improved Correlated Prefetching
with A. Jain
46th International Symposium on Microarchitecture (Micro),
2013, pp. 247-259.
(Finalist, Best Paper Award)
Dynamic Scheduling for Large-Scale Distributed-Memory Ray Tracing
with P. Navratil, H. Childs, and D. Fussell
Eurographics Symposium on Parallel Graphics and Visualization,
2012.
(Best Paper Award)
Flow-Sensitive Pointer Analysis for Millions of Lines of Code
with B. Hardekopf
International Symposium on Code Generation and Optimization (CGO),
2011, pp. 289--298.
(Best Paper Award)
(2023 CGO Test of Time Award)
The Ant and the Grasshopper: Fast and Accurate Pointer Analysis
for Millions of Lines of Code
with Ben Hardekopf
ACM Conference on Programming Language Design and Implementation (PLDI),
June, 2007, pp. 290-299.
(Best Paper Award)
Adaptive History-Based Memory Schedulers
with Ibrahim Hur
37th International Symposium on Microarchitecture (Micro),
December, 2004, pp. 343-354.
(Best Paper Award)
Dynamic Branch Prediction with Perceptrons
with D. Jiménez
Proceedings of the 7th Int'l Symposium on High
Performance Computer Architecture (HPCA),
January, 2001. pp. 197-206.
(2019 HPCA Test of Time Award)
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Teaching
