Calvin Lin
    Professor of Computer Science
    University of Texas, Austin
 
   
 
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  Conference and Workshop Papers

  • A New Formulation of Neural Data Prefetching
    with Q. Duong and A. Jain.
    International Symposium on Computer Architecture (ISCA), 2024

  • Tail Victims in Termination Timing Channel Protections beyond Cryptographic Kernels
    with S. Wei, A. Harris, Y. Zhu, P. Ramrakhyani, and M. Tiwari,
    International Symposium on Secure and Private Execution Environment Design (SEED), 2024

  • Leveraging Domain Information for the Efficient, Automated Design of Deep Learning Accelerators
    with C. Sakhuja and Z. Shi,
    International Symposium on High-Performance Computer Architectural (HPCA), 2023

  • Effective Mimicry of Belady's MIN Policy
    with I. Shah and A. Jain,
    International Symposium on High-Performance Computer Architectural (HPCA), 2022
    (Micro Top Picks 2023)
    (Finalist, Best Paper Award)

  • A Hierarchical Neural Model of Data Prefetching
    with Z. Shi, A. Jain, K. Swersky, M. Hashemi, and P. Raganathan,
    International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2020
    (Micro Top Picks Honorable Mention)

  • A Fast Work-Efficient SSSP Algorithm for GPUs
    with K. Wang and D. Fussell,
    26th Annual Symposium on Principles and Practice of Parallel Programming (PPoPP), 2020

  • Combining Branch History and Value History For Improved Value Prediction,
    with C. Sakhuja, A. Subramanian, P. Joshi, and A. Jain,
    2nd Championship Value Prediction (Top Place Unlimited Category), 2019

  • A Neural Hierarchical Sequence Model for Irregular Data Prefetching
    with Z. Shi, A. Jain, K. Swersky, M. Hashemi, and P. Ranganathan.
    ML for Systems Workshop at NeurIPS, 2019.

  • Temporal Prefetching without the Off-Chip Metadata
    with H. Wu, K. Nathella, J. Pusdesris, D. Sunwoo, and A. Jain,
    52nd International Symposium on Microrchitecture (MICRO), 2019, pp. 996-1008.

  • Applying Deep Learning to the Cache Replacement Problem
    with Z. Shi, X. Huang, and A. Jain,
    52nd International Symposium on Microrchitecture (MICRO), 2019, pp. 413-425.

  • Efficient Metadata Management for Irregular Data Prefetching
    with H. Wu, K. Nathella, D. Sunwoo, and A. Jain
    46th International Symposium on Computer Architecture (ISCA), 2019, pp. 449-461.

  • Fast Fine-Grained Global Synchronization on GPUs
    with K. Wang and D. Fussell
    24th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) 2019, pp. 793-806.

  • Rethinking Belady's Algorithm to Accommodate Prefetching
    with A. Jain
    45th International Symposium on Computer Architecture (ISCA), 2018, pp. 110-123.

  • Static Detection of Asymptotic Resource Side-Channel Vulnerabilities in Web Application
    with J. Chen, O. Olivo, and I. Dillig
    Int'l Conference Automated Software Engineering (ASE) 2017, pp. 229-239.

  • Hawkeye: Leveraging Belady's Algorithm for Improved Cache Replacement
    with A. Jain
    2nd Cache Replacement Competition, 2017.
    (First Place Finisher)

  • Decoupled Affine Computation for SIMT GPUs
    with K. Wang
    44th International Symposium on Computer Architecture (ISCA), 2017, pp. 295--306.

  • Secure, Precise, and Fast Floating-Point Operations on x86 Processors
    with A. Rane and M. Tiwari
    25th USENIX Security Symposium (USENIX Security) 2016, pp. 71-86.

  • Back to the Future: Leveraging Belady's Algorithm for Improved Cache Replacement
    with A. Jain
    43th International Symposium on Computer Architecture (ISCA), 2016, pp. 78-89.
    (Micro Top Picks Honorable Mention)

  • CS Teacher Experiences with Educational Technology, Problem-Based Learning, and a CS Principles Curriculum
    with G. Veletsianos and B. Beth,
    ACM Technical Symposium on Computer Science Education (SIGCSE), 2016, pp. 651-656.

  • Detecting and Exploiting Second Order Denial-of-Service Vulnerabilities in Web Applications
    with O. Olivo and I. Dillig
    ACM Conference on Computer and Communications Security (CCS), 2015, pp. 616-628.

  • Explorer: Query- and Demand-Driven Exploration of Interprocedural Control Flow Properties
    with Y. Feng, X. Wang, and I. Dillig
    ACM Conference on Object-Oriented Programming, Systems, Languages, and Applications (OOPSLA), 2015, pp. 520-534.

  • Raccoon: Closing Digital Side-Channels through Obfuscated Execution
    with A. Rane and M. Tiwari
    USENIX Security Symposium, 2015, pp. 431-446.

  • Static Detection of Asymptotic Performance Bugs in Collection Traversals
    with O. Olivo and I. Dillig
    ACM Conference on Programming Language Design and Implementation (PLDI), 2015, pp. 369-378.

  • A Structured Approach to Teaching Recursion Using Cargo-Bot
    with E. Lee, V. Shan, and B. Beth
    International Computing Education Research Conference (ICER), 2014, pp. 59-66.

  • Linearizing Irregular Memory Accesses for Improved Correlated Prefetching
    with A. Jain
    46th IEEE/ACM International Symposium on Microarchitecture (Micro), 2013, pp. 247-259.
    (Finalist, Best Paper Award)

  • Using Cargo-Bot to Provide Contextualized Learning of Recursion
    with J. Tessler and B. Beth
    International Computing Education Research Workshop (ICER), 2013, pp. 161-168.

  • Using Peer Review to Teach Software Testing
    with J. Smith, J. Tessler, and E. Kramer
    International Computing Education Research Workshop (ICER), 2012, pp. 93-98.

  • Dynamic Scheduling for Large-Scale Distributed-Memory Ray Tracing
    with P. Navratil, H. Childs, and D. Fussell
    Eurographics Symposium on Parallel Graphics and Visualization, 2012, pp. 61-70.
    (Best Paper Award)

  • A Scalable Algorithm for Compiler-Placed Staggered Checkpointing
    with A. Norman,
    IASTED International Conference on Parallel and Distributed Computing and Systems, 2011, pp. 1-8.

  • Flow-Sensitive Pointer Analysis for Millions of Lines of Code
    with B. Hardekopf
    International Symposium on Code Generation and Optimization (CGO), 2011, pp. 289--298.
    (Best Paper Award)
    (2023 CGO Test of Time Award)

  • Semi-Sparse Flow-Sensitive Pointer Analysis
    with Ben Hardekopf
    Symposium on Principles of Programming Languages (POPL), 2009, pp. 226-238.

  • Feedback Mechanisms for Improving Probabilistic Memory Prefetching
    with Ibrahim Hur
    International Symposium on High-Performance Computer Architecture (HPCA), February 2009, pp. 443-454.

  • Efficient and Extensible Security Enforcement Using Dynamic Data Flow Analysis
    with Walter Chang and Brandon Streiff
    Computer and Communications Security (CCS), 2008, pp. 39-50.

  • A Comprehensive Approach to DRAM Power Management
    with Ibrahim Hur
    International Symposium on High-Performance Computer Architecture (HPCA), February, 2008, pp. 305-316.
    (Finalist, Best Paper Award)

  • Dynamic Ray Scheduling to Improve Ray Coherence and Bandwidth Utilization
    with Paul Navratil, Don Fussell, and Bill Mark
    Symposium on Interactive Ray Tracing September, 2007, pp. 95-104.

  • Exploiting Pointer and Location Equivalence to Optimize Pointer Analysis
    with Ben Hardekopf
    2007 Static Analysis Symposium (SAS), August, 2007, pp. 265-280.

  • The Ant and the Grasshopper: Fast and Accurate Pointer Analysis for Millions of Lines of Code
    with Ben Hardekopf
    ACM Conference on Programming Language Design and Implementation (PLDI), June, 2007, pp. 290-299.
    (Best Paper Award)

  • Memory Prefetching Using Adaptive Stream Detection
    with Ibrahim Hur
    39th International Symposium on Microarchitecture (Micro), December, 2006, pp. 397-408.
    (Finalist, Best Paper Award)

  • Efficient Flow-Sensitive Interprocedural Data-flow Analysis in the Presence of Pointers
    with Teck Bok Tok and Samuel Z. Guyer
    Compiler Construction (CC), Springer-Verlag LNCS 3923, 2006, pp. 17-31.

  • Fault Aware Instruction Placement for Static Architectures
    with Premkishore Shivakumar, Divya P. Gulati, and Stephen W. Keckler 1st Workshop on High Performance Computing Reliability Issues, February, 2005.

  • Adaptive History-Based Memory Schedulers
    with Ibrahim Hur
    37th International Symposium on Microarchitecture (Micro), December, 2004, pp. 343-354.
    (Best Paper Award)

  • Compiler-Generated Staggered Checkpointing
    with Alison N. Norman and Sung-Eun Choi
    7th ACM Workshop on Languages, Compilers, and Runtime Support for Scalable Systems (LCR), October, 2004.

  • Static Placement, Dynamic Issue (SPDI) Scheduling for EDGE Architectures
    with Ramadass Nagarajan, Sundeep K. Kushwaha, Doug Burger, Stephen W. Keckler, Kathryn S. McKinley
    Int'l Conference on Parallel Architectures and Compilation Techniques (PACT), October, 2004, pp. 74-84.

  • Client-Driven Pointer Analysis
    with S. Guyer
    10th Annual International Static Analysis Symposium (SAS), June, 2003. pp. 214-236.

  • Using Mixins to Build Flexible Widgets
    with R. Cardone, A. Brown, and S. McDirmid
    1st International Conference on Aspect-Oriented Software Development April, 2002. pp. 76-85.

  • Branch Path Re-aliasing
    with D. Jiménez
    4th ACM Workshop on Feedback-Directed and Dynamic Optimization, December, 2001. pp. 83-92.

  • Boolean Formula-based Branch Prediction for Future Technologies
    with D. Jiménez and H.L. Hanson
    Int'l Conference on Parallel Architectures and Compilation Techniques (PACT), September, 2001. pp. 97-106.

  • Perceptron Learning for Predicting the Behavior of Conditional Branches
    with Daniel Jiménez
    Proceedings of the INNS-IEEE International Joint Conference on Neural Networks (IJCNN). June, 2001. pp. 2122-2126.

  • Customizing Software Libraries for Performance Portability
    with E. Berger and S. Guyer
    10th SIAM Conference on Parallel Processing for Scientific Computing, March, 2001.

  • Comparing Frameworks and Layered Refinement
    with R. Cardone
    Proceedings of the 23rd Int'l Conference on Software Engineering (ICSE), May, 2001. pp. 285-294.

  • Dynamic Branch Prediction with Perceptrons
    with D. Jiménez
    Proceedings of the 7th Int'l Symposium on High Performance Computer Architecture (HPCA), January, 2001. pp. 197-206.
    (2019 HPCA Test of Time Award)

  • The Impact of Delay on the Design of Branch Predictors
    with D. Jiménez and S. Keckler.
    Proceedings of the 33rd International Symposium on Microarchitecture (Micro), December, 2000. pp. 67-76.

  • Broadway: A Software Architecture for Scientific Computing
    with S. Guyer
    The Architecture of Scientific Software, R.F. Boisvert and P.T.P. Tang, editors, Kluwer Academic Press, 2000, pp. 175-192.

  • Optimizing the Use of High Performance Software Libraries
    with S. Guyer
    Languages and Compilers for Parallel Computing, S. Midkiff, J. Moreira, M. Gupta, S. Chatterjee, J. Ferrante, J. Prins, W. Pugh, and C. Tseng eds. Springer-Verlag 2002, pp. 227-243.

  • Modeling the Cache Effects of Interprocessor Communication
    with I.Hur
    Parallel and Distributed Computing and Systems (PDCS'99), November, 1999, pp. 938-943. (Long version in submission).

  • An Annotation Language for Optimizing Software Libraries
    with S.Guyer
    Second Conference on Domain Specific Languages, October, 1999, pp. 39-53.

  • Hierarchical Cache Consistency in a WAN
    with J.Yin, L. Alvisi, and M. Dahlin
    Second USENIX Symposium on Internet Technologies and Systems, October, 1999, pp, 13-24.

  • Regions: An Abstraction for Expressing Array Computation
    with B. Chamberlain, E. Lewis, and L. Snyder
    ACM International Conference on Array Programming Languages, August, 1999, pp. 41-49.

  • Using Leases to Support Server-Driven Consistency in Large-Scale Systems
    with J.Yin, L. Alvisi, and M. Dahlin
    Proceedings of the 18th IEEE International Conference on Distributed Computing Systems, Amsterdam, The Netherlands, May 1998, pp. 285-294.

  • The Implementation and Evaluation of Fusion and Contraction in Array Languages
    with E Lewis and L. Snyder
    1998 ACM SIGPLAN Conference on Programming Language Design and Implementation, Montreal, June 1998, pp 50-59.

  • A Flexible Class of Parallel Matrix Multiplication Algorithms
    with J. Gunnels, G. Morrow and R. van de Geijn
    12th International Parallel Processing Symposium and 9th Symposium on Parallel and Distributed Processing, Orlando, March 1998.

  • ZPL's WYSIWYG Performance Model
    with B. Chamberlain, S. Choi, E Lewis, L. Snyder and W. Weathersby
    Third International Workshop on High-Level Parallel Programming Models and Suportive Environments, Orlando, March 1998, pp. 50-61.

  • Seuss: What the Doctor Ordered
    with L. Alvisi, R. Joshi, and J. Misra
    Second International Workshop on Software Engineering for Parallel and Distributed Systems, Boston, 1997, pp 284-290.

  • Factor-Join: A Unique Approach to Compiling Array Languages for Parallel Machines
    with B. Chamberlain, S. Choi, E. Lewis, L. Snyder, and W. Weathersby
    Languages and Compilers for Parallel Computing, D. Sehr, U. Banerjee, D. Gelernter, A. Nicolau and D. Padua eds., Springer-Verlag 1996, pp. 481-500.

  • Parallel Performance of a Meshless Method for Wind Engineering Simulations
    with G. Turkiyyah, D. Reed, and C. Viozat
    Proceedings of the 12th Conference on Analysis and Computation, 1996, pp. 177-187.

  • The Portable Parallel Implementation of Two Novel Mathematical Biology Algorithms in ZPL
    with M. D. Dikaiakos, D. Manoussaki, and D. Woodward
    9th Int'l Conf. on Supercomputing, Barcelona, 1995, pp. 365-374.

  • A Portable Parallel N-Body Solver
    with E. Lewis, L. Snyder and G. Turkiyyah
    Proceedings of the 7th SIAM Conference on Parallel Processing for Scientific Computing, San Francisco, 1995, pp 231-236.

  • SIMPLE Performance Results in ZPL
    with L. Snyder
    Languages and Compilers for Parallel Computing, K. Pingali, U. Banerjee, D. Gelernter, A. Nicolau and D. Padua eds., Springer-Verlag 1994, pp. 361-375.

  • Accommodating Polymorphic Data Decompositions in Explicitly Parallel Programs
    with L. Snyder
    8th International Parallel Processing Symposium, Cancun, April 1994, pp. 68-74.

  • ZPL: An Array Sublanguage
    with L. Snyder
    Languages and Compilers for Parallel Computing, U. Banerjee, D. Gelernter, A. Nicolau and D. Padua eds., Springer-Verlag 1994, pp. 96-11.

  • Towards a Machine-Independent Solution of Sparse Cholesky Factorization
    with W. Weathersby
    Parallel Computing 93, Grenoble, France, September 1993.

  • The Ariadne Debugger: Scalable Application of Event-Based Abstraction
    with J. Cuny, G. Forman, A. Hough, J. Kundu, L. Snyder and D. Stemple
    1993 ACM/ONR Workshop on Parallel and Distributed Debugging, San Diego, CA, May 1993, pp. 85-95.

  • Data Ensembles in Orca C
    with L. Snyder
    Languages and Compilers for Parallel Computing, U. Banerjee, D. Gelernter, A. Nicolau and D. Padua eds., Springer-Verlag 1993, pp. 112-123.

  • Programming SIMPLE for Parallel Portability
    with L. Snyder
    Languages and Compilers for Parallel Computing, U. Banerjee, D. Gelernter, A. Nicolau and D. Padua eds., Springer-Verlag 1992, pp. 84-98.

  • Portable Parallel Programming: Cross Machine Comparisons for SIMPLE
    with L. Snyder
    Proceedings of the 5th SIAM Conference on Parallel Processing for Scientific Computing, Houston, 1991, pp 564-569.

  • A Comparison of Programming Models for Shared Memory Multiprocessors
    with L. Snyder
    Proceedings of the 1990 International Conference on Parallel Processing, St. Charles, IL, 1990, pp II:163-170.
    • Journal Publications

  • Practical Temporal Prefetching With Compressed On-Chip Metadata
    with H. Wu, K. Nathella, M. Pabst, D. Sunwoo, and A. Jain
    IEEE Transactions on Computers, Special Issue on Highlights of Computer Architecture, 2021.

  • Design Principles for Thriving in Our Digital World
    with G. Veletsianos, B. Beth, and G. Russell
    Journal of Educational Computing Research, 54(4), July, 2016, pp. 443-461.

  • Training a Diverse Computer Science Teacher Population
    with B. Beth and G. Veletsianos
    ACM Inroads, 6(4), December, 2015, pp. 94-97.

  • Exploring the Spectrum of Dynamic Scheduling Algorithms for Scalable Distributed-Memory Ray Tracing
    with P. Navratil, H. Childs, and D. Fussell
    IEEE Transactions on Visualization and Computer Graphics, 20(6), June, 2014, pp. 893-906.

  • Memory Scheduling for Modern Microprocessors
    with I. Hur
    ACM Transactions on Computer Systems, 25(4), December, 2007, pp. 10-46.

  • Adaptive History-Based Memory Schedulers for Modern Microprocessors
    with I. Hur
    IEEE Micro "Top picks issue," vol 26(1), 2006, pp. 22-29.

  • Error Checking with Client-Driven Pointer Analysis
    with Samuel Z. Guyer
    Science of Computer Programming Journal, vol 58, 2005, pp. 83-114.

  • Broadway: A Compiler for Exploiting the Domain-Specific Semantics of Software Libraries
    with Samuel Z. Guyer
    Proceedings of the IEEE, Special issue on program generation, optimization, and adaptation. 93(2), 2005, pp. 342-357.

  • Scaling to the End of Silicon with EDGE Architectures
    with D. Burger, S. Keckler, M. Dahlin, L. John, K. McKinley, C. Moore, J. Burrill, R. McDonald, and W. Yoder.
    IEEE Computer, 37(7), July, 2004, pp. 44-55.

  • Neural Methods for Dynamic Branch Prediction
    with Daniel Jiménez
    ACM Transactions on Computer Systems, 20(4), November 2002, pp. 369-397.

  • ZPL: A Machine Independent Programming Language for Parallel Computers
    with B. Chamberlain, S. Choi, E. Lewis, L. Snyder, and W. Weathersby
    IEEE Transactions on Software Engineering, 26(3), March 2000. Special Issue on Architecture-Independent Languages and Software Tools for Parallel Processing. pp. 197-211.

  • Volume Leases for Consistency in Large-Scale Systems
    with J.Yin, L. Alvisi, and M. Dahlin
    IEEE Transactions on Knowledge and Data Engineering, 11(4), July/August 1999. pp. 563-577.

  • The Case for High Level Parallel Programming in ZPL
    with B. Chamberlain, S. Choi, E. Lewis, L. Snyder, and W. Weathersby
    IEEE Computational Science and Engineering, 5(3), July-September 1998, pp. 76-86.

  • Abstractions for Portable, Scalable Parallel Programming
    with G. Alverson, W. Griswold, D. Notkin and L. Snyder
    IEEE Trans. on Parallel and Distributed Systems, 9(1), 1998, pp. 1-17.

  • A Portable Implementation of SIMPLE
    with Lawrence Snyder
    International Journal of Parallel Programming, 20(5), 1991, pp. 363-401.

    • Books

  • Cache Replacement Policies
    with A. Jain
    Morgan & Claypool, 2019.

  • Principles of Parallel Programming
    with L. Snyder
    Addison-Wesley, ISBN-10: 0321487907, 2008.

    • Book Chapters

  • Using Mixin Technology To Improve Modularity
    with R. Cardone
    Aspect-Oriented Software Development, Mehmet Aksit, Siobhan Clarke, Tzilla Elrad, and Richard Filman, eds. Addison-Wesley, 2003. pp. 219-242.

    • Theses

  • Incorporating Prior Knowledge to Efficiently Design Deep Learning Accelerators. (Chirag Sakhuja, PhD Thesis, 2024).

  • Improving Efficiency for GPUs with Decoupled Delegate. (Kai Wang, PhD Thesis, 2020).

  • Machine Learning for Prediction Problems in Computer Architecture. (Zhan Shi, PhD Thesis, 2020).

  • Practical Irregular Prefetching. (Hao Wu, PhD Thesis, 2020).

  • Advancing Value Prediction. (Anjana Subramanian, MS Thesis, 2019).

  • Techniques for Advancing Value Prediction. (Pawan Joshi, MS Thesis, 2019).

  • Broad-Based Side-Channel Defenses for Modern Microprocessors. (Ashay Rane, PhD Thesis, 2019).

  • Program Analysis Techniques for Algorithmic Complexity and Relational Properties. (Jia Chen, PhD Thesis, 2019).

  • Exploiting Long-Term Behavior for Improved Memory System Performance. (Akanksha Jain, PhD Thesis, 2016).

  • Automatic Static Analysis of Software Performance. (Oswaldo Olivo, PhD Thesis, 2016).

  • Enabling High-Performance, Mixed-Signal Approximate Computing . (Renee St. Amant, PhD Thesis, 2014).

  • Jack Rabbit: An Effective Cell BE Programming System for High Performance Parallelism. (Apollo Ellis, MS Thesis, 2011).

  • Memory-Efficient, Scalable Ray Tracing. (Paul Navratíl, PhD Thesis, 2010).

  • A Proposed Memory Consistency Model for Chapel. (Karthik Murthy, MS Thesis, 2010).

  • Compiler-Assisted Staggered Checkpointing. (Alison Norman, PhD Thesis, 2010).

  • Improving Dynamic Analysis with Data Flow Analysis. (Walter Chang, PhD Thesis, 2010).

  • Pointer Analysis: Building a Foundation for Effective Program Analysis. (Ben Hardekopf, PhD Thesis, 2009).

  • Removing Unimportant Computations in Interprocedural Program Analysis. (Teck Bok Tok, PhD Thesis, 2007).

  • Enhancing Memory Controllers to Improve DRAM Power and Performance. (Ibrahim Hur, PhD Thesis, 2006).

  • Incorporating Domain-Specific Information into the Compilation Process. (Samuel Z. Guyer, PhD Thesis, 2003).

  • Language and Compiler Support for Mixin Programming. (Richard J. Cardone, PhD Thesis, 2002).

  • Delay-Sensitive Branch Predictors for Future Technologies. (Daniel A. Jiménez, PhD Thesis, 2002).

  • Software Methods for Avoiding Cache Conflicts. (Frank Kuehndel, MS Thesis, 1998).

  • A Comparison of Metaphoric Global Optimization Techniques. (Kent Spaulding, MS, Plan III, Software Quality Institute Thesis, 1998).
    •   Last updated: April 29, 2024