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CFG.
See:
Description
| Class Summary | |
|---|---|
| BeginMarker | This class marks the first position in a routine. |
| BlockSplitter | This class can determine if a block is a legal TRIPS block and can cut a block so that it meets the TRIPS block constraints. |
| ConstantInstruction | This class represents Trips non-branch instructions for generating large constants. |
| DataflowAnalysis | This class computes liveness on the Hyperblock Flow Graph. |
| EnterInstruction | This class represents pseudo instruction ENTER. |
| GeneralInstruction | This class represents Trips non-branch three operand instructions. |
| Hyperblock | This class represents a hyperblock which represents a predicate flow graph. |
| HyperblockFormation | Backend hyperblock formation. |
| ImmediateInstruction | This class represents Trips non-branch instructions with an immediate operand. |
| LoadInstruction | This class represents Trips load instructions. |
| Opcodes | This class provides Trips instruction information. |
| Peepholer | This is the Peephole optimizer for TRIPS. |
| PhiInstruction | This class represents pseudo instruction Phi for building SSA form. |
| PredicateBlock | This class represents a predicated basic block. |
| SSA | This class converts a PFG into the SSA form of the PFG. |
| StoreInstruction | This class represents Trips store instructions. |
| TILReader | This class reads a TRIPS IL file (.til). |
| Trips2Allocator | This class implements a quick and dirty register allocator for the Trips TIL. |
| Trips2AllocatorHybrid | This class implements a hybrid version of the trips register allocator. |
| Trips2Assembler | This class generates Trips assembly language from a list of Trips instructions. |
| Trips2Generator | This class converts Scribble into TRIPS instructions. |
| Trips2LineMarker | This class is used to associate source line numbers with instructions. |
| Trips2Machine | This is the base class for all Trips specific information. |
| Trips2RegisterSet | This class describes the register set of the TRIPS Grid Processor. |
| TripsBranch | This class represents Trips branch instructions. |
| TripsInstruction | This class represents a Trips instruction. |
| TripsIntrinsics | This class represents Trips intrinsic functions. |
| TripsLabel | This class marks the position of a point branched to in Trips code. |
| TripsLoopICEstimator | This class estimates instruction counts for TRIPS loops. |
| TripsPGenerator | This class converts PTIL into TRIPS instructions. |
The Trips backend for the Scale compiler generates Trips Intermediate
Language (TIL) files for the Trips processor
from the Scale CFG. These files are then
read by the Trips scheduler which schedules the instructions to the
processors on the grid. It is the Trips scheduler that actually
outputs Trips assembly language files.
The following documents are avilable from the University of Texas at Austin Computer Science Department:
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